riversongs Posted March 12 Report Share Posted March 12 Free Download Udemy - Design Verification With Systemverilog/UVMPublished: 3/2025MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHzLanguage: English | Size: 12.89 GB | Duration: 21h 19mUnveiling UVM in SystemVerilog Language: From Building UVM Agents to Functional Coverage and Debugging TechniquesWhat you'll learnModule level verification using SystemVerilog and UVM library.Build agents in SystemVerilog/UVM to drive and monitor communication interfaces.Build the model of the registers using UVM and connect it to the APB interface in order to let UVM perform its automatic checks on the register accesses.Build the functional model of a Device Under Test (DUT) and use it to predict the correct response expected from the DUT.Build a scoreboard to verify automatically all the expected outputs of a DUT.Build the coverage model and all the logic necessary to collect that coverage.Build random tests to verify all the features of a DUT.Learn how to deal with synchronization issues in the model.RequirementsYou need to have a basic understanding of digital integrated circuits and how they are modeled in a HDL language like Verilog.There is no hard requirement for your to know SystemVerilog but prior OOP and Verilog knowledge is required.DescriptionMaster UVM Library & Create a Verification Environment: Comprehensive Course OverviewIn this course, you'll delve into two crucial areas:UVM Library: Uncover all its features, secrets, and how they can be applied effectively in verification environments.Verification Environment Creation: Learn the step-by-step process of building a robust verification environment from the ground up using UVM.Course Objectives:Throughout this course, we'll guide you through the development of a verification environment, meticulously designed using the UVM library. Each tutorial will introduce new functionalities, demonstrating the UVM features necessary for each phase of our comprehensive project.We'll leverage the EDA Playground platform to develop our verification environment. By the end of the course, our final project will encompass over 5000 lines of code, providing a substantial showcase of your acquired skills and knowledge.By the end of this course, you will master:Building UVM agents and understanding their rolesModeling design registers using the UVM librarySetting up a Device Under Test (DUT) within a verification environmentVerifying the outputs of a DUT to ensure accuracy and functionalityImplementing functional coverage in SystemVerilog to achieve thorough verificationWriting and executing random tests to cover a wide range of scenariosEmploying advanced debugging techniques to identify and resolve issuesExploring and utilizing hidden features of the UVM library to enhance your projectsThe skills you gain from this course will not only prepare you for entry or junior-level verification engineer job interviews but will also ensure you are productive and effective from day one in your new role.OverviewSection 1: IntroductionLecture 1 IntroductionLecture 2 What is Design VerificationLecture 3 Device Under Test (DUT)Lecture 4 Environment ArchitectureLecture 5 Environment Coding Kick Off - LectureLecture 6 Environment Coding Kick off - Practice - InfoLecture 7 Environment Coding Kick Off - PracticeSection 2: The Basics in Building an UVM AgentLecture 8 APB Agent Infrastructure - LectureLecture 9 APB Agent Infrastructure - Practice - InfoLecture 10 APB Agent Infrastructure - PracticeLecture 11 APB Driving Item - LectureLecture 12 APB Driving Item - Practice - InfoLecture 13 APB Driving Item - PracticeLecture 14 APB Sequence Mechanism - LectureLecture 15 APB Sequence Mechanism - Practice - InfoLecture 16 APB Sequence Mechanism - PracticeLecture 17 APB Driver - LectureLecture 18 APB Driver - Practice - InfoLecture 19 APB Driver - PracticeLecture 20 APB Monitor - LectureLecture 21 APB Monitor - Practice - InfoLecture 22 APB Monitor - PracticeLecture 23 APB Protocol Checks - LectureLecture 24 APB Protocol Checks - Practice - InfoLecture 25 APB Protocol Checks - PracticeLecture 26 APB Coverage - LectureLecture 27 APB Coverage - Practice - InfoLecture 28 APB Coverage - PracticeLecture 29 APB Reset Handling - LectureLecture 30 APB Reset Handling - Practice - InfoLecture 31 APB Reset Handling - PracticeLecture 32 APB Agent - ConclusionsSection 3: Building Reusable UVM AgentsLecture 33 Memory Data (MD) ProtocolLecture 34 MD Agent ArchitectureLecture 35 MD Agent Infrastructure - LectureLecture 36 MD Agent Infrastructure- Practice - InfoLecture 37 MD Agent Infrastructure - PracticeLecture 38 MD Master Driving Logic - LectureLecture 39 MD Master Driving Logic - Practice - InfoLecture 40 MD Master Driving Logic - PracticeLecture 41 MD Monitor - LectureLecture 42 MD Monitor - Practice - InfoLecture 43 MD Monitor - PracticeLecture 44 MD Slave Driving Logic - LectureLecture 45 MD Slave Driving Logic - Practice - InfoLecture 46 MD Slave Driving Logic - PracticeLecture 47 MD Protocol Checks - LectureLecture 48 MD Protocol Checks - Practice - InfoLecture 49 MD Protocol Checks - PracticeLecture 50 MD Coverage - LectureLecture 51 MD Coverage - Practice - InfoLecture 52 MD Coverage - PracticeLecture 53 MD Agent - ConclusionsSection 4: Advanced Technique For Building UVM AgentsLecture 54 Advanced Technique for Building UVM Agents - IntroductionLecture 55 UVM Extension Agent Configuration - LectureLecture 56 UVM Extension Agent Configuration - Practice - InfoLecture 57 UVM Extension Agent Configuration - PracticeLecture 58 UVM Extension Monitor - LectureLecture 59 UVM Extension Monitor - Practice - InfoLecture 60 UVM Extension Monitor - PracticeLecture 61 UVM Extension Coverage - LectureLecture 62 UVM Extension Coverage - Practice - InfoLecture 63 UVM Extension Coverage - PracticeLecture 64 UVM Extension Sequencer - LectureLecture 65 UVM Extension Sequencer - Practice - InfoLecture 66 UVM Extension Sequencer - PracticeLecture 67 UVM Extension Driver - LectureLecture 68 UVM Extension Driver - Practice - InfoLecture 69 UVM Extension Driver - PracticeLecture 70 UVM Extension Agent - LectureLecture 71 UVM Extension Agent - Practice - InfoLecture 72 UVM Extension Agent - PracticeLecture 73 UVM Extension Package - ConclusionsSection 5: UVM Register ModelLecture 74 UVM Register Model - IntroductionLecture 75 UVM Register Field - LectureLecture 76 UVM Register - LectureLecture 77 UVM Register Field and UVM Register - Practice - InfoLecture 78 UVM Register Field and UVM Register - PracticeLecture 79 UVM Register Block - LectureLecture 80 UVM Register Block - Practice - InfoLecture 81 UVM Register Block - PracticeLecture 82 Integration with Bus Monitor - LectureLecture 83 Integration with Bus Monitor - Practice - InfoLecture 84 Integration with Bus Monitor - PracticeLecture 85 Custom Register Predictor - LectureLecture 86 Custom Register Predictor - Practice - InfoLecture 87 Custom Register Predictor - PracticeLecture 88 Integration with Bus Sequencer - LectureLecture 89 Integration with Bus Sequencer - Practice - InfoLecture 90 Integration with Bus Sequencer - PracticeLecture 91 Register Field Callback - LectureLecture 92 Register Field Callback - Practice - InfoLecture 93 Register Field Callback - PracticeLecture 94 UVM Register Model - ConclusionsSection 6: Modeling and CheckingLecture 95 Modeling and Checking - IntroductionLecture 96 Model ArchitectureLecture 97 Model Interface - LectureLecture 98 Model Interface - Practice - InfoLecture 99 Model Interface - PracticeLecture 100 Model Illegal RX Accesses - LectureLecture 101 Model Illegal RX Accesses - Practice - InfoLecture 102 Model Illegal RX Accesses - PracticeLecture 103 Model Legal RX Accesses - LectureLecture 104 Model Legal RX Accesses - Practice - InfoLecture 105 Model Legal RX Accesses - PracticeLecture 106 Model Intermediate Buffer - LectureLecture 107 Model Intermediate Buffer - Practice - InfoLecture 108 Model Intermediate Buffer - PracticeLecture 109 Model Align Logic - LectureLecture 110 Model Align Logic - Practice - InfoLecture 111 Model Align Logic - PracticeLecture 112 Model TX Controller - LectureLecture 113 Model TX Controller - Practice - InfoLecture 114 Model TX Controller - PracticeLecture 115 Scoreboard ArchitectureLecture 116 Scoreboard Interface - LectureLecture 117 Scoreboard Interface - Practice - InfoLecture 118 Scoreboard Interface - PracticeLecture 119 Scoreboard Check: RX Response - LectureLecture 120 Scoreboard Check: RX Response - Practice - InfoLecture 121 Scoreboard Check: RX Response - PracticeLecture 122 Scoreboard Check: TX Item - LectureLecture 123 Scoreboard Check: TX Item - Practice - InfoLecture 124 Scoreboard Check: TX Item - PracticeLecture 125 Scoreboard Check: IRQ - LectureLecture 126 Scoreboard Check: IRQ - Practice - InfoLecture 127 Scoreboard Check: IRQ - PracticeLecture 128 Model Synchronization: FIFO Flags - LectureLecture 129 Model Synchronization: FIFO Flags - Practice - InfoLecture 130 Model Synchronization: FIFO Flags - PracticeLecture 131 Model Synchronization: Push & Pop - LectureLecture 132 Model Synchronization: Push & Pop - Practice - InfoLecture 133 Model Synchronization: Push & Pop - PracticeLecture 134 Model Synchronization: Overlapping IRQs - LectureLecture 135 Model Synchronization: Overlapping IRQs - Practice - InfoLecture 136 Model Synchronization: Overlapping IRQs - PracticeLecture 137 DUT Functional Coverage - LectureLecture 138 DUT Functional Coverage - Practice - InfoLecture 139 DUT Functional Coverage - PracticeLecture 140 Virtual Sequencer - LectureLecture 141 Virtual Sequencer - Practice - InfoLecture 142 Virtual Sequencer - PracticeLecture 143 Modeling and Checking - ConclusionsSection 7: Debug and TestsLecture 144 Debug and Tests - IntroductionLecture 145 UVM Messages - LectureLecture 146 UVM Messages - Practice - InfoLecture 147 UVM Messages - PracticeLecture 148 UVM TransactionsLecture 149 Debugging Technique: Track the SourceLecture 150 Tests OrganizationLecture 151 Tests: Register Access - LectureLecture 152 Tests: Register Access - Practice - InfoLecture 153 Tests: Register Access - PracticeLecture 154 Tests: Random Traffic - LectureLecture 155 Tests: Random Traffic - Practice - InfoLecture 156 Tests: Random Traffic - PracticeLecture 157 Tests: Illegal RX Traffic - LectureLecture 158 Tests: Illegal RX Traffic - Practice - InfoLecture 159 Tests: Illegal RX Traffic - PracticeLecture 160 Debug and Tests - ConclusionsSection 8: Wrapping UpLecture 161 Stages of a Verification ProjectLecture 162 OutroStudents and engineers who want to learn how to do module level verification using SystemVerilog language and UVM library.Homepage: https://www.udemy.com/course/design-verification-with-systemverilog-uvm/ Rapidgator Links Downloadhttps://rg.to/file/0c6632be4e688ff03ec6557b1f662a5e/vlfqn.Design.Verification.With.SystemverilogUvm.part01.rar.htmlhttps://rg.to/file/65af5b2bf3760657c57ef669a5a9260e/vlfqn.Design.Verification.With.SystemverilogUvm.part02.rar.htmlhttps://rg.to/file/1ea91701b86e6848e1a040b8668b8981/vlfqn.Design.Verification.With.SystemverilogUvm.part03.rar.htmlhttps://rg.to/file/5c360bf1f763f5773ef92dd4b9770f54/vlfqn.Design.Verification.With.SystemverilogUvm.part04.rar.htmlhttps://rg.to/file/e8969d3be5084e6e1ee3e7d655c71fc2/vlfqn.Design.Verification.With.SystemverilogUvm.part05.rar.htmlhttps://rg.to/file/6b99cc6a6f7f67e604100d0caa294bf3/vlfqn.Design.Verification.With.SystemverilogUvm.part06.rar.htmlhttps://rg.to/file/677d750e50c10d2dfdafd3c61d75e44c/vlfqn.Design.Verification.With.SystemverilogUvm.part07.rar.htmlhttps://rg.to/file/19f21a9b79c08ea890e1db10b1b800b7/vlfqn.Design.Verification.With.SystemverilogUvm.part08.rar.htmlhttps://rg.to/file/dd575fb02ea51ffdfdc89b68b58f70af/vlfqn.Design.Verification.With.SystemverilogUvm.part09.rar.htmlhttps://rg.to/file/66dfd22969f2bedae65b7f41982ef33f/vlfqn.Design.Verification.With.SystemverilogUvm.part10.rar.htmlhttps://rg.to/file/68b863d0233b08326523d4f8a92cadf6/vlfqn.Design.Verification.With.SystemverilogUvm.part11.rar.htmlhttps://rg.to/file/bb3820b00233926a05738d2660f1d13a/vlfqn.Design.Verification.With.SystemverilogUvm.part12.rar.htmlhttps://rg.to/file/1a0510e31f11c88c79b6f56a6c875c04/vlfqn.Design.Verification.With.SystemverilogUvm.part13.rar.htmlhttps://rg.to/file/bf64efb4d00f84fd106bd70e9187a647/vlfqn.Design.Verification.With.SystemverilogUvm.part14.rar.htmlFikper Links Downloadhttps://fikper.com/H44VwlGLUC/vlfqn.Design.Verification.With.SystemverilogUvm.part01.rar.htmlhttps://fikper.com/1ztMvV3fN9/vlfqn.Design.Verification.With.SystemverilogUvm.part02.rar.htmlhttps://fikper.com/Ys1Fpc2KyG/vlfqn.Design.Verification.With.SystemverilogUvm.part03.rar.htmlhttps://fikper.com/6pA3u7RX97/vlfqn.Design.Verification.With.SystemverilogUvm.part04.rar.htmlhttps://fikper.com/MLOyEvkiQv/vlfqn.Design.Verification.With.SystemverilogUvm.part05.rar.htmlhttps://fikper.com/FVIfqCH5qu/vlfqn.Design.Verification.With.SystemverilogUvm.part06.rar.htmlhttps://fikper.com/NPvpaEciXn/vlfqn.Design.Verification.With.SystemverilogUvm.part07.rar.htmlhttps://fikper.com/fhHIlu5CUz/vlfqn.Design.Verification.With.SystemverilogUvm.part08.rar.htmlhttps://fikper.com/Y8wL1tcrio/vlfqn.Design.Verification.With.SystemverilogUvm.part09.rar.htmlhttps://fikper.com/hss7UVFPjT/vlfqn.Design.Verification.With.SystemverilogUvm.part10.rar.htmlhttps://fikper.com/7kcm3GEpdE/vlfqn.Design.Verification.With.SystemverilogUvm.part11.rar.htmlhttps://fikper.com/qKAGlKp74w/vlfqn.Design.Verification.With.SystemverilogUvm.part12.rar.htmlhttps://fikper.com/BF6sXoyIcb/vlfqn.Design.Verification.With.SystemverilogUvm.part13.rar.htmlhttps://fikper.com/DGtR14GGnd/vlfqn.Design.Verification.With.SystemverilogUvm.part14.rar.htmlNo Password - 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