SystemVerilog Verification -1: Start Learning TB Constructs

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SystemVerilog Verification -1: Start Learning TB Constructs

MP4 | Video: AVC 1280x720 | Audio: AAC 44KHz 2ch | Duration: 1.5 Hours | Lec: 21 | 173 MB

Genre: eLearning | Language: English

 

VLSI : Learn Systemverilog - Begin your System Verilog learning from the basics to build expertise in SOC verification

 

This course contains video lectures of 1 hour duration. It is stared by explaining what is design and verification code in System Verilog and how they are different.

 

VLSI : Learn Systemverilog - Begin your System Verilog learning from the basics to build expertise in SOC verification

This System Verilog course teaches the System-On-Chip design verification used in VLSI industry. This will be a good starting point to learn System-Verilog language for IC/SOC verification. It covers the fundamentals of the language and explain the concepts from the basics.

This course contains video lectures of 1 hour duration. It is stared by explaining what is design and verification code in System Verilog and how they are different. It explains the language constructs like datatypes, arrays and operators in next session with examples. Different kind of assignments in SV are explained in detail with their behavior in simulation. The control flow statements and looping statements are demonstrated in the next session. Finally, the thread launching mechanism is explained at the end

By taking this course, the a student will be able to start learning System Verilog for verification and master it slowly. This course will also be helpful for the HDL programmers who know something about SV programming but not clear about its structured writing.

 

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